This invention relates to semiconductor devices and a method of making the devices, and, more particularly, to a semiconductor memory device having a static random access memory and a method of making the same.
A conventional highly-integrated static random access memory (SRAM) using insulated gate field effect transistors (IGFET's: hereinafter referred to as MOS transistors which are most typical) has a construction as shown in an equivalent circuit of FIG. 2A. This SRAM comprises a flip-flop circuit having two driver MOS transistors T1 and T2 coupled with each other in cross connection, highly resistive elements R1 and R2 for supplying extremely small currents to two store nodes N1 and N2 of the flip-flop circuit so as to store data connected to the store nodes N1 and N2, and transfer MOS transistors T3 and T4 for "write" and "read" of data which is to be connected to or which has been connected to the store nodes N1 and N2.
The flip-flop circuit is supplied with standard voltages such as power supply voltage Vcc and grounded potential GND, and the transfer MOS transistors are connected with data lines 1 and 1', having their gates connected in common to a word line 2.
As well known in the art, such a SRAM cell operates as follows More particularly, when the word line 2 is activated to, typically, higher potential, "high" or "low" data from the data lines are stored at the store nodes N1 and N2 through the transfer MOS transistors or conversely, statuses of the store nodes are read out to the data lines.
At present, the above type of memory cell having four MOS transistors and two highly resistive elements is used as a highly-integrated SRAM cell of the most general type. Recently, however, to ensure low-power consumption operations at low voltage, MOS transistors formed on a polycrystalline silicon layer have been used in place of the highly resistive load.
FIG. 2B diagrammatically shows a planar configuration of the conventional memory cell comprised of the four MOS transistors and two highly resistive elements. In the figure, gate electrodes 5b and 5c correspond to the gate electrodes of the driver MOS transistors T1 and T2 shown in FIG. 2A and a gate electrode 5a corresponds to the common gate, serving as the word line, of the transfer MOS transistors T3 and T4 shown in FIG. 2A. A highly concentrated n-type impurity region 3d serving as the drain of the driver MOS transistor T1 is in common to an n-type impurity region of the transfer MOS transistor T3.
A highly concentrated n-type impurity region 3e serving as the drain of the driver MOS transistor T2 is electrically connected, at the bottom of a contact hole 8a, to an n-type impurity region 3c of the transfer MOS transistor T4 by the gate electrode 5b. The contact hole 8a intervenes between the gate electrode 5b and a low resistivity polycrystalline silicon layer 9a.
The gate electrode 5c of the driver MOS transistor T2 is connected to the n-type impurity region 3d common to the transfer MOS transistor T3 and driver MOS transistor T1 to establish the cross connection in the flip-flop circuit of the static random access memory cell.
Contact holes 6a and 6b are respectively opened through highly concentrated n-type impurity regions 3f and 3g serving as the sources of the driver MOS transistors T1 and T2 to ensure electrical connection of the sources to a second layer in the form of a conductive layer 7.
Standard voltage is supplied to the sources of the driver MOS transistors T1 and T2 through this conductive layer 7. In order to prevent grounded potential from being raised by current flowing in the memory cell, the second layer acting as the conductive layer 7 is formed of a composite film (polycide film) having a low resistive polycrystalline silicon layer and a refractory silicide layer.
Contact holes 8a and 8b are respectively opened through the gate electrodes 5b and 5c, and highly resistive polycrystalline silicon layers 9c and 9d are connected to the gate electrodes 5b and 5c through low resistivity polycrystalline silicon layers 9a and 9b. A low resistivity polycrystalline silicon layer 9e serves as a common power supply electrode for feeding power supply voltage to the highly resistive polycrystalline silicon layers.
Aluminum electrodes 11a and 11b correspond to the two data lines in the memory cell, and they are electrically connected to highly concentrated n-type impurity regions 3a and 3b of the transfer MOS transistors T4 and T3 through contact holes 10a and 10b.
The prior art as discribed above is disclosed in, for example, JP-A-63-29576 which corresponds to an anterior application by the present applicant, and it features that the area of an electrode in a cell for standard potential supply connected to the memory cell can be reduced and the degree of integration of SRAM can be improved.
U.S. patent application Ser. No. 07/503,928 by some of the present inventors pertains to a SRAM.